01
The qualification question
What evidence is required before an agent-generated electrical design can be trusted with fabrication data, money, and a physical build?
Bench Revision A tested a narrow version of that question. It is a low-voltage controller board with a microcontroller, power conversion, watchdog, supervisor, current sensing, switching, protection, connectors, and a reset switch. The board is useful because its failures cross electrical, physical, mechanical, assembly, and tool boundaries.
The sprint did not prove autonomous PCB design. It established a more useful result: native checks can show that the represented files are internally legal while leaving the represented component or physical current path wrong.
02
What was built
The output is not one final board. It is an inspectable progression from requirements and exact parts to native EDA, failed routes, independent checks, and an explicit fabrication stop.
01
Requirements and authority
The workflow records the intended supply, load, interfaces, fault behaviour, operating conditions, and owner decisions before treating the design as a release candidate.
Open inputs stop release
02
Exact component identity
Each important part must bind one orderable MPN to reviewed pin meaning, symbol, footprint, package geometry, source conditions, and mechanical orientation.
MPN to physical package
03
Native electrical design
The case generated a native schematic and PCB for a 12 V, one-channel controller bench, then retained each material routing and placement state for comparison.
Editable KiCad source
04
Independent checks
ERC, DRC, and schematic parity are combined with part, pad, placement, current-loop, artifact, and deliberate-fault checks that do not rely on the same generated assumption.
Native plus semantic
05
Release and physical test
An accepted route, reconciled manufacturing package, owner approval, incoming inspection, staged bring-up, and measured behaviour remain required before a board can support a physical claim.
Not reached
Release rule
A successful process log is telemetry. An accepted result requires a clean exit, a durable output, a recorded hash, a successful import, and independent post-import checks.
03
What failed
The strongest failure was a route that looked finished and passed its native checks.
Candidate 1 completed all 133 open connections with zero DRC violations, zero unconnected items, and zero schematic-parity differences. Electrical review then measured an approximately 85.2 mm path from the regulator input to its input capacitor, alongside long switch and feedback paths, timing vias, and inadequate local ground transfer. The route was rejected.
| State | Observed result | Decision |
|---|---|---|
| Pre-audit export | Full-looking package with invalid component assumptions | Quarantined |
| Candidate 1 | Complete route and clean native checks; poor physical paths | Rejected |
| Candidates 2–6 | Critical copper, crossings, shorts, stalls, or open connections | Preserved as failures |
| Candidate 7 | Corrected clean seed; route-session save repeatedly failed | Frozen unrouted |
Visual progression / exact archived KiCad output / no AI-generated imagery
01 / Candidate 1 / rejected routeAll 133 declared connections completed, and native DRC and parity passed. Electrical review rejected the approximately 85.2 mm regulator input-capacitor path and other critical geometry. Red is the KiCad copper plot, not a failure overlay. 
02 / Candidate 7 / qualification seedCorrected component identity, orientation, and placement with no routed copper. The frozen check records 109 expected open connections because no global route was accepted. 
03 / Candidate 7 / mechanical viewThe later view exposes package seating, connector direction, Pico USB access, and component height. It is a render of the same unrouted seed, not a photograph or manufacturing proof.
These exact, hash-matched images came from the append-only sprint archive. They are pre-fabrication observations from source, tool output, and board geometry—not photographs or measurements from assembled hardware.
04
The missing component contract
A part number, symbol, footprint, and 3D body cannot remain independent clues. The system needs one versioned object for each exact orderable part.
Several early defects survived because two generated artifacts agreed with the same wrong assumption. A two-pad reset-switch abstraction agreed with its PCB but did not match the four physical terminals. A regulator net map was correct while its first land pattern used the wrong pitch. A connector was electrically legal while its 3D service direction was wrong.
| Contract area | Required evidence |
|---|---|
| Identity and source | Exact MPN, variant, revision, hash, page or figure locator |
| Electrical meaning | Physical pins, symbol pins, limits, conditions, and exceptions |
| CAD and geometry | Native symbol, footprint, pad set, package, STEP model, and previews |
| Manufacturing and supply | Orientation, process notes, lifecycle, supplier codes, and alternates |
| Authority | Rights, validator results, review state, mutations, and physical uses |
Next module
Open the schemas, rights-aware records, validators, preview generators, failure corpus, and neutral manufacturing format. Keep customer data, licensed feeds, vendor credentials, laboratory evidence, and the orchestrator inside the operated service.
05
Evidence at the 13 July 2026 sprint freeze
The archive preserves successes, rejected routes, timeouts, missing outputs, images, source states, and deliberate fault tests. The counts below describe the local case record; they do not certify the board.
What the 958,091-line PCB corpus contains
The measured scale is real, but calling it 958,091 lines of code would be misleading. Most retained lines are generated design geometry and exact archived states kept so failures remain inspectable.
- Maintained source, tests, inputs, and notes
- 2,970 lines / 0.31%
- Active generated EDA and verification
- 227,383 lines / 23.73%
- Append-only iteration archive
- 647,126 lines / 67.54%
- Active vendor and tool assets
- 80,612 lines / 8.41%
Counted from every Git-tracked text file in the Bench Revision A workspace at the sprint freeze; binary images and models are excluded. The maintained material includes 2,681 physical Python lines across four board scripts and one semantic-test module. This is a retained engineering corpus, not an authorship measure.
| Layer | Evidence | State |
|---|---|---|
| Candidate 7 native seed | 0 placement/copper violations; 0 parity differences; 109 expected opens | Checked |
| Semantic contract | 13 critical parts; 57 BOM rows; 49 populated SMD placements; 18 pad sets | Pass |
| Deliberate fault mutations | 4 incorrect states rejected | Pass |
| Iteration archive | 20 events; 216 artifacts; 41,310,214 bytes | Hash verified |
| Frozen-source reproduction | Generator changed after the seed and was not rerun | Open |
| Accepted Candidate 7 route | No route-session file exists | Open |
| Physical proof | No order, assembly, power-on, or test | Not started |
The active manufacturer directory contains only a fabrication-stop marker. The superseded output is retained in the evidence archive, where it cannot be mistaken for a current release.
06
The next campaign
The next useful milestone is not more ad hoc routing. It is a harness that can explain and reject the same failures before a release exists.
01
Qualify the component contract
Build one versioned evidence package per exact MPN, including source locators, pin meaning, native CAD, package geometry, STEP model, rights, review state, and known-good use.
13 critical parts
02
Generate inspectable previews
Render symbol, footprint, pinout, and 3D views, then test pad sets, pin-one orientation, model origin, seating plane, body envelope, and service direction.
Symbol to STEP
03
Encode physical layout intent
Measure switch loops, bootstrap attachment, Kelvin sense, bypass returns, thermal copper, creepage, connector access, and rework space independently of the router.
Current loops and returns
04
Make tool runs reproducible
Run KiCad and routing adapters in recorded environments with immutable inputs, timeouts, exit checks, save-and-reload transactions, hashes, and automatic release invalidation.
Clean inputs and outputs
05
Route and review again
Treat routing as a replaceable search step. Accept its output only after the file persists, imports cleanly, passes native and semantic checks, and satisfies the physical measurements.
Accepted copper
06
Build the physical feedback loop
Export a manufacturer-neutral package, rehearse manual ingestion, then fabricate one low-risk revision and capture inspection, bring-up, thermal, transient, and fault evidence.
Owner approval required
Manufacturing release gate
No active fabrication package exists
Quote, upload, order creation, payment, and tracking are separate future capabilities. Each requires explicit authority. No manufacturer partnership or live integration is claimed.
07
Selected sources
- KiCad 10 command-line interface
Native ERC, DRC, schematic parity, and manufacturing export interface.
- KiCad libraries license
License and design-output exception for the component models visible in the archived KiCad renders.
- Diodes Incorporated: AP63200/AP63201/AP63203/AP63205 datasheet
Pin functions, package drawing, layout guidance, and operating limits.
- Texas Instruments: SN74AHCT123A datasheet
Watchdog pin functions, timing network, and logic behaviour.
- Raspberry Pi Pico datasheet
Module pin assignments, power connections, and mechanical dimensions.
- Littelfuse/C&K: PTS815 series datasheet
Four-terminal contact arrangement and recommended land pattern.
- PCBSchemaGen: reward-guided schematic synthesis with verification
Version 2 related work on converting circuit intent into validated schematic data.
- Component-centric placement for PCB layouts
Related work on component-level structure in automated PCB placement.
08
Read Working Paper 01.
The complete ten-page paper turns the sprint record into a pre-fabrication qualification argument. It is published for public review, not presented as peer-reviewed research or proof of physical hardware.
Public review draft / Not peer reviewed